This paper introduces a 71.2-$\mu$W speech recognition accelerator designed for edge devices' real-time applications, emphasizing an ultra low power design. Achieved through algorithm and hardware co-optimizations, we propose a compact recurrent spiking neural network with two recurrent layers, one fully connected layer, and a low time step (1 or 2). The 2.79-MB model undergoes pruning and 4-bit fixed-point quantization, shrinking it by 96.42\% to 0.1 MB. On the hardware front, we take advantage of \textit{mixed-level pruning}, \textit{zero-skipping} and \textit{merged spike} techniques, reducing complexity by 90.49\% to 13.86 MMAC/S. The \textit{parallel time-step execution} addresses inter-time-step data dependencies and enables weight buffer power savings through weight sharing. Capitalizing on the sparse spike activity, an input broadcasting scheme eliminates zero computations, further saving power. Implemented on the TSMC 28-nm process, the design operates in real time at 100 kHz, consuming 71.2 $\mu$W, surpassing state-of-the-art designs. At 500 MHz, it has 28.41 TOPS/W and 1903.11 GOPS/mm$^2$ in energy and area efficiency, respectively.

翻译：本文介绍了一种专为边缘设备实时应用设计的71.2微瓦语音识别加速器，其设计重点在于超低功耗。通过算法与硬件的协同优化，我们提出了一种紧凑的循环脉冲神经网络，该网络包含两个循环层、一个全连接层，并采用低时间步长（1或2）。该2.79 MB的模型经过剪枝和4位定点量化，尺寸缩减了96.42%至0.1 MB。在硬件层面，我们利用了*混合级剪枝*、*零跳过*和*合并脉冲*技术，将计算复杂度降低了90.49%至13.86 MMAC/S。*并行时间步执行*解决了时间步间的数据依赖问题，并通过权重共享实现了权重缓冲区的功耗节省。利用脉冲活动的稀疏性，一种输入广播方案消除了零值计算，进一步节省了功耗。该设计基于台积电28纳米工艺实现，在100 kHz频率下实时运行，功耗为71.2微瓦，性能超越了现有先进设计。在500 MHz频率下，其能效和面积效率分别为28.41 TOPS/W和1903.11 GOPS/mm²。