When modern FPGA architecture becomes increasingly complicated, modern FPGA placement is a mixed optimization problem with multiple objectives, including wirelength, routability, timing closure, and clock feasibility. Typical FPGA devices nowadays consist of heterogeneous SLICEs like SLICEL and SLICEM. The resources of a SLICE can be configured to {LUT, FF, distributed RAM, SHIFT, CARRY}. Besides such heterogeneity, advanced FPGA architectures also bring complicated constraints like timing, clock routing, carry chain alignment, etc. The above heterogeneity and constraints impose increasing challenges to FPGA placement algorithms. In this work, we propose a multi-electrostatic FPGA placer considering the aforementioned SLICEL-SLICEM heterogeneity under timing, clock routing and carry chain alignment constraints. We first propose an effective SLICEL-SLICEM heterogeneity model with a novel electrostatic-based density formulation. We also design a dynamically adjusted preconditioning and carry chain alignment technique to stabilize the optimization convergence. We then propose a timing-driven net weighting scheme to incorporate timing optimization. Finally, we put forward a nested Lagrangian relaxation-based placement framework to incorporate the optimization objectives of wirelength, routability, timing, and clock feasibility. Experimental results on both academic and industrial benchmarks demonstrate that our placer outperforms the state-of-the-art placers in quality and efficiency.

翻译：随着现代FPGA架构日趋复杂，现代FPGA布局成为涉及线长、可布线性、时序收敛与时钟可行性的多目标混合优化问题。当前典型FPGA器件包含如SLICEL与SLICEM等异构SLICE单元，单个SLICE的资源可配置为{LUT、FF、分布式RAM、SHIFT、CARRY}。除此类异构性外，先进FPGA架构还引入时序约束、时钟布线、进位链对齐等复杂约束，上述异构性与约束给FPGA布局算法带来日益严峻的挑战。本文提出一种多静电场FPGA布局器，在时序、时钟布线与进位链对齐约束下，综合考虑前述SLICEL-SLICEM异构性。首先，基于静电场构建新型密度公式，提出有效的SLICEL-SLICEM异构性模型。其次，设计动态调整预处理与进位链对齐技术以稳定优化收敛过程。再次，提出时序驱动的线网加权方案以融入时序优化。最终，提出基于嵌套拉格朗日松弛的布局框架，整合线长、可布线性、时序与时钟可行性等优化目标。在学术和工业基准测试上的实验结果表明，本布局器在质量和效率上均优于现有最优布局器。