For critical applications that require a higher level of reliability, the Triple Modular Redundancy (TMR) scheme is usually employed to implement fault-tolerant arithmetic units. However, this method imposes a significant area and power/energy overhead. Also, the majority-based voter in the typical TMR designs is highly sensitive to soft errors and the design diversity of the triplicated module, which may result in an error for a small difference between the output of the TMR modules. However, a wide range of applications deployed in critical systems are inherently error-resilient, i.e., they can tolerate some inexact results at their output while having a given level of reliability. In this paper, we propose a High Precision Redundancy Multiplier (HPR-Mul) that relies on the principles of approximate computing to achieve higher energy efficiency and lower area, as well as resolve the aforementioned challenges of the typical TMR schemes, while retaining the required level of reliability. The HPR-Mul is composed of full precision (FP) and two reduced precision (RP) multipliers, along with a simple voter to determine the output. Unlike the state-of-the-art Reduced Precision Redundancy multipliers (RPR-Mul) that require a complex voter, the voter of the proposed HPR-Mul is designed based on mathematical formulas resulting in a simpler structure. Furthermore, we use the intermediate signals of the FP multiplier as the inputs of the RP multipliers, which significantly enhance the accuracy of the HPR-Mul. The efficiency of the proposed HPR-Mul is evaluated in a 15-nm FinFET technology, where the results show up to 70% and 69% lower power consumption and area, respectively, compared to the typical TMR-based multipliers. Also, the HPR-Mul outperforms the state-of-the-art RPR-Mul by achieving up to 84% higher soft error tolerance.

翻译：对于需要更高可靠性的关键应用，通常采用三模冗余（TMR）方案来实现容错算术单元。然而，该方法会带来显著的面积和功耗/能量开销。此外，典型TMR设计中的多数表决器对软错误和三个复制模块的设计多样性高度敏感，即使TMR模块输出之间存在微小差异也可能导致错误。然而，部署在关键系统中的大量应用本身具有误差弹性，即它们可以在保持给定可靠性水平的同时，容忍输出结果存在一定的不精确性。本文提出了一种高精度冗余乘法器（HPR-Mul），它基于近似计算原理，在保持所需可靠性水平的同时，实现了更高的能效和更小的面积，并解决了典型TMR方案的上述挑战。HPR-Mul由一个全精度（FP）乘法器和两个缩减精度（RP）乘法器以及一个简单的表决器组成，用于确定输出。与需要复杂表决器的最新缩减精度冗余乘法器（RPR-Mul）不同，所提出的HPR-Mul的表决器基于数学公式设计，结构更为简单。此外，我们使用FP乘法器的中间信号作为RP乘法器的输入，这显著提高了HPR-Mul的精度。所提出的HPR-Mul在15纳米FinFET工艺中进行了效能评估，结果表明，与典型的基于TMR的乘法器相比，其功耗和面积分别降低了高达70%和69%。同时，HPR-Mul通过实现高达84%的软错误容忍度提升，性能优于最新的RPR-Mul。