Fault injection attacks exploit physical disturbances to compromise the functionality and security of integrated circuits. As System on Chip (SoC) architectures grow in complexity, the vulnerability of on chip communication fabrics has become increasingly prominent. Buses, serving as interconnects among various IP cores, represent potential vectors for fault-based exploitation. In this study, we perform simulation-driven fault injection across three mainstream bus protocols Wishbone, AXI Lite, and AXI. We systematically examine fault success rates, spatial vulnerability distributions, and timing dependencies to characterize how faults interact with bus-level transactions. The results uncover consistent behavioral patterns across protocols, offering practical insights for both attack modeling and the development of resilient SoC designs.

翻译：故障注入攻击利用物理扰动破坏集成电路的功能与安全性。随着片上系统（SoC）架构日益复杂，片上通信结构的脆弱性愈发凸显。作为连接各IP核的互连总线，其本身可能成为基于故障的攻击载体。本研究通过仿真驱动的故障注入方法，对三种主流总线协议——Wishbone、AXI-Lite与AXI——进行了系统性分析。我们系统考察了故障注入成功率、空间脆弱性分布及时序依赖性，以刻画故障如何与总线级事务交互。研究结果揭示了跨协议的一致性行为模式，为攻击建模与鲁棒性SoC设计提供了实用见解。