We present LearnedFTL, a new on-demand page-level flash translation layer (FTL) design, which employs learned indexes to improve the address translation efficiency of flash-based SSDs. The first of its kind, it reduces the number of double reads induced by address translation in random read accesses. LearnedFTL proposes three key techniques: an in-place-update linear model to build learned indexes efficiently, a virtual PPN representation to obtain contiguous PPNs for sorted LPNs, and a group-based allocation and model training via GC/rewrite strategy to reduce the training overhead. By tightly integrating the aforementioned key techniques, LearnedFTL considerably speeds up address translation while reducing the number of flash read accesses caused by the address translation. Our extensive experiments on a FEMU-based prototype show that LearnedFTL can reduce up to 55.5\% address translation-induced double reads. As a result, LearnedFTL reduces the P99 tail latency by 2.9$\times$ $\sim$ 12.2$\times$ with an average of 5.5$\times$ and 8.2$\times$ compared to the state-of-the-art TPFTL and LeaFTL schemes, respectively.

翻译：我们提出了LearnedFTL，一种新的按需页级闪存转换层（FTL）设计，它利用学习型索引来提升闪存SSD的地址转换效率。作为同类首个方案，它减少了随机读访问中由地址转换引起的双重读取次数。LearnedFTL提出了三项关键技术：用于高效构建学习型索引的原位更新线性模型、为已排序LPN获取连续PPN的虚拟PPN表示，以及通过GC/重写策略实现的分组分配与模型训练，以降低训练开销。通过紧密集成上述关键技术，LearnedFTL显著加速了地址转换，同时减少了由地址转换引发的闪存读访问次数。我们在基于FEMU的原型系统上进行了大量实验，结果表明，LearnedFTL可减少高达55.5%的地址转换引起的双重读取。因此，与当前最先进的TPFTL和LeaFTL方案相比，LearnedFTL的P99尾部延迟分别降低了2.9倍至12.2倍，平均降低5.5倍和8.2倍。