Caches at CPU nodes in disaggregated memory architectures amortize the high data access latency over the network. However, such caches are fundamentally unable to improve performance for workloads requiring pointer traversals across linked data structures. We argue for accelerating these pointer traversals closer to disaggregated memory, in a manner that preserves expressiveness for supporting various linked structures, ensures energy efficiency and performance, and supports distributed execution. We design ADPDM to meet all the above requirements for pointer-traversal workloads on rack-scale disaggregated memory through the principled use of FPGAbased SmartNICs and programmable network switches. Our evaluation of ADPDM shows that it enables low-latency, highthroughput, and energy-efficient execution for a wide range of common pointer traversal workloads on disaggregated memory that fare poorly with caching alone.

翻译：在分解内存架构中，CPU节点上的缓存能够分摊网络上的高数据访问延迟。然而，这类缓存本质上无法改善需要跨链接数据结构进行指针遍历的工作负载的性能。我们主张在更靠近分解内存的位置加速这些指针遍历，同时保持表达力以支持各种链接结构，确保能效与性能，并支持分布式执行。我们设计了ADPDM，通过基于FPGA的智能网卡和可编程网络交换机的原则性使用，满足以上在机架级分解内存上的指针遍历工作负载的所有要求。对ADPDM的评估表明，对于在分解内存上仅靠缓存效果不佳的各类常见指针遍历工作负载，它能够实现低延迟、高吞吐量和节能的执行。