Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue. Recent analytical methods typically use pin-level timing information to adjust net weights, which is fast and simple but neglects the path-based nature of the timing graph. The existing path-based methods, however, cannot balance the accuracy and efficiency due to the exponential growth of number of critical paths. In this work, we propose a GPU-accelerated timing-driven global placement framework, integrating accurate path-level information into the efficient DREAMPlace infrastructure. It optimizes the fine-grained pin-to-pin attraction objective and is facilitated by efficient critical path extraction. We also design a quadratic distance loss function specifically to align with the RC timing model. Experimental results demonstrate that our method significantly outperforms the current leading timing-driven placers, achieving an average improvement of 40.5% in total negative slack (TNS) and 8.3% in worst negative slack (WNS), as well as an improvement in half-perimeter wirelength (HPWL).

翻译：集成电路全局布局中的时序优化数十年来一直是重要研究方向，但仍是复杂且尚未完全解决的难题。当前分析方法通常采用引脚级时序信息调整线网权重，这种方法快速简便，却忽略了时序图固有的路径特性。而现有基于路径的方法由于关键路径数量呈指数增长，难以平衡精度与效率。本研究提出一种GPU加速的时序驱动全局布局框架，将精确的路径级信息集成至高效的DREAMPlace基础设施中。该框架通过高效关键路径提取机制，优化细粒度引脚间引力目标函数。我们还专门设计了与RC时序模型匹配的二次距离损失函数。实验结果表明，本方法显著优于当前领先的时序驱动布局工具，在总负时序裕量（TNS）和最大负时序裕量（WNS）上分别平均提升40.5%和8.3%，同时优化了半周长线长（HPWL）。