Reduced voltage operation is an effective technique for substantial energy efficiency improvement in digital circuits. This brief introduces a simple approach for enabling reduced voltage operation of Deep Neural Network (DNN) accelerators by mere software modifications. Conventional approaches for enabling reduced voltage operation e.g., Timing Error Detection (TED) systems, incur significant development costs and overheads, while not being applicable to the off-the-shelf components. Contrary to those, the solution proposed in this paper relies on algorithm-based error detection, and hence, is implemented with low development costs, does not require any circuit modifications, and is even applicable to commodity devices. By showcasing the solution through experimenting on popular DNNs, i.e., LeNet and VGG16, on a GPU platform, we demonstrate 18% to 25% energy saving with no accuracy loss of the models and negligible throughput compromise (< 3.9%), considering the overheads from integration of the error detection schemes into the DNN. The integration of presented algorithmic solution into the design is simpler when compared conventional TED based techniques that require extensive circuit-level modifications, cell library characterizations or special support from the design tools.

翻译：降低电压运行是提升数字电路能效的有效技术。本文介绍一种仅通过软件修改即可实现深度神经网络（DNN）加速器降压运行的简易方法。传统的降压运行实现方案（如时序错误检测系统）需付出高昂的开发成本与性能开销，且无法直接应用于现成硬件组件。与此不同，本文提出的解决方案基于算法级错误检测机制，因而能以较低开发成本实现，无需任何电路修改，甚至可适用于商用设备。通过在GPU平台上对主流DNN模型（LeNet与VGG16）进行实验验证，我们证明在集成错误检测方案产生开销的情况下，该方法可实现18%至25%的能耗节约，且模型精度无损失，吞吐量影响可忽略不计（<3.9%）。相较于需要大量电路级修改、单元库特征化或设计工具特殊支持的传统时序错误检测技术，本算法方案与系统设计的集成过程更为简便。