The increasing number of rectilinear floorplans in modern chip designs presents significant challenges for traditional macro placers due to the additional complexity introduced by blocked corners. Particularly, the widely adopted wirelength model Half-Perimeter Wirelength (HPWL) struggles to accurately handle rectilinear boundaries, highlighting the need for additional objectives tailored to rectilinear floorplan optimization. In this paper, we identify the necessity for whitespace diagnosis in rectilinear floorplanning, an aspect often overlooked in past research. We introduce WISP, a novel framework that analyzes and scores whitespace regions to guide placement optimization. WISP leverages image segmentation techniques for whitespace parsing, a lightweight probabilistic model to score whitespace regions based on macro distribution, a Gaussian Mixture Model (GMM) for whitespace density scoring and direction-aware macro relocation to iteratively refine macro placement, reduce wasted whitespace, and enhance design quality. The proposed diagnostic technique also enables the reclamation of block-level unused area and its return to the top level, maximizing overall area utilization. When compared against state-of-the-art academia placer DREAMPlace 4.1, our method achieves an average improvement of 5.4% in routing wirelength, with a maximum of 11.4% across widely-used benchmarks. This yields an average of 41.5% and 43.7% improvement in Worst Negative Slack (WNS) and Total Negative Slack (TNS), respectively. Additionally, WISP recycles an average of 16.2% area at the block level, contributing to more efficient top-level area distribution.

翻译：现代芯片设计中直角多边形布图数量的不断增加，由于阻塞角落引入的额外复杂性，给传统宏单元布局器带来了重大挑战。特别是广泛采用的线长模型半周长线长（HPWL）难以准确处理直角多边形边界，凸显了需要针对直角多边形布图优化定制额外目标。本文指出了直角多边形布图规划中空白区域诊断的必要性，这是过去研究中常被忽视的方面。我们提出了WISP，一种通过分析并评分空白区域来指导布局优化的新颖框架。WISP利用图像分割技术进行空白区域解析，采用轻量级概率模型基于宏单元分布对空白区域评分，运用高斯混合模型（GMM）进行空白区域密度评分，并结合方向感知的宏单元重定位来迭代优化宏单元布局、减少空白区域浪费并提升设计质量。所提出的诊断技术还能回收模块级未利用区域并将其返还至顶层，最大化整体面积利用率。与学术界最先进的布局器DREAMPlace 4.1相比，我们的方法在广泛使用的基准测试中平均降低了5.4%的布线线长，最高达11.4%。这分别在最差负时序裕量（WNS）和总负时序裕量（TNS）上实现了平均41.5%和43.7%的改善。此外，WISP平均回收了16.2%的模块级面积，有助于实现更高效的顶层面积分配。