Routing is a crucial step in the VLSI design flow. With the advancement of manufacturing technologies, more constraints have emerged in design rules, particularly regarding obstacles during routing, leading to increased routing complexity. Unfortunately, many global routers struggle to efficiently generate obstacle-free solutions due to the lack of scalable obstacle-avoiding tree generation methods and the capability of handling modern designs with complex obstacles and nets. In this work, we propose an efficient obstacle-aware global routing flow for VLSI designs with obstacles. The flow includes a rule-based obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) algorithm during the tree generation phase. This algorithm is both scalable and fast to provide tree topologies avoiding obstacles in the early stage globally. With its guidance, OARSMT-guided and obstacle-aware sparse maze routing are proposed in the later stages to minimize obstacle violations further and reduce overflow costs. Compared to advanced methods on the benchmark with obstacles, our approach successfully eliminates obstacle violations, and reduces wirelength and overflow cost, while sacrificing only a limited number of via counts and runtime overhead.

翻译：布线是VLSI设计流程中的关键步骤。随着制造技术的进步，设计规则中出现了更多约束，尤其是布线过程中的障碍物，这导致布线复杂性显著增加。遗憾的是，由于缺乏可扩展的避障树生成方法以及处理具有复杂障碍物与线网的现代设计的能力，许多全局布线器难以高效生成无冲突的布线方案。在本工作中，我们提出了一种面向含障碍物VLSI设计的高效避障全局布线流程。该流程在树生成阶段包含一种基于规则的避障直角斯坦纳最小树（OARSMT）算法。该算法兼具可扩展性与高速度，能在全局布线早期阶段提供避开障碍物的树形拓扑结构。在其指导下，我们在后续阶段提出了OARSMT引导的避障稀疏迷宫布线方法，以进一步最小化障碍物违规并降低溢流代价。与先进方法在含障碍物基准测试上的对比表明，我们的方法成功消除了障碍物违规，减少了线长与溢流代价，同时仅牺牲了有限数量的通孔数量与运行时间开销。