Modern computer architecture relies heavily on simulation to identify bottlenecks and evaluate optimizations. However, existing microarchitectural performance analysis methods are fundamentally limited by an instruction-centric paradigm that captures only downstream symptoms while leaving the true microarchitectural root cause opaque. Because modern processors are governed by complex interactions across non-instruction entities like prefetchers, replacement policies, and shared queue occupancies, instruction-centric frameworks miss the mechanisms that dictate performance. To eliminate this blind spot, we present Microflow, a framework that achieves causal observability in microarchitectural simulation. To address this, we introduce the Microflow intermediate representation (MFIR), which models execution through microarchitecture-tailored core abstractions such as flows, resource tenancies, and causal edges. By compiling simulation runs into a relational causal database, Microflow decouples tracing from analytical processing. This transforms complex diagnostics into expressive queries, enabling architects to trace performance symptoms directly to hardware root causes without developing bespoke analysis scripts or running costly re-simulations for every new question. We demonstrate that Microflow solves pathologies opaque to conventional tools. Across CVP-1 benchmarks, Microflow decomposes a 22% prefetcher oracle headroom by attributing 61.4% of stall mass to specific hardware prefetcher decisions, yielding a 2.31% average speedup (peaking at 25.11%). Furthermore, it exposes the hidden pipeline-blocking residue of wrong-path execution with high portability and precision across simulators.

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