Systolic arrays and shared L1-memory manycore clusters are commonly used architectural paradigms that offer different trade-offs to accelerate parallel workloads. While the first excel with regular dataflow at the cost of rigid architectures and complex programming models, the second are versatile and easy to program but require explicit data flow management and synchronization. This work aims at enabling efficient systolic execution on shared L1-memory manycore clusters. We devise a flexible architecture where small and energy-efficient RISC-V cores act as the systolic array's processing elements (PEs) and can form diverse, reconfigurable systolic topologies through queues mapped in the cluster's shared memory. We introduce two low-overhead RISC-V ISA extensions for efficient systolic execution, namely Xqueue and Queue-linked registers (QLRs), which support queue management in hardware. The Xqueue extension enables single-instruction access to shared-memory-mapped queues, while QLRs allow implicit and autonomous access to them, relieving the cores of explicit communication instructions. We demonstrate Xqueue and QLRs in MemPool, an open-source manycore cluster with 256 PEs, and analyze the hybrid systolic-shared-memory architecture's trade-offs on matrix multiplication, convolution, and FFT kernels. For an area increase of just 6%, our hybrid architecture almost doubles MemPool's compute unit utilization to up to 95% and significantly improves energy efficiency, achieving up to 63% of power spent in the PEs. In typical conditions (TT/0.80V/25{\deg}C) in a 22nm FDX technology, our hybrid architecture runs at 600MHz with no frequency degradation and is up to 64% more energy efficient than the shared-memory baseline, achieving up to 208GOPS/W.

翻译：脉动阵列和共享L1内存多核集群是常用的架构范式，它们通过不同的权衡方式来加速并行工作负载。前者虽然擅长规则数据流，但代价是架构僵化且编程模型复杂；后者虽然灵活易编程，但需要显式的数据流管理与同步。本研究旨在实现共享L1内存多核集群上的高效脉动执行。我们设计了一种灵活架构，将小型高能效RISC-V核作为脉动阵列的处理单元（PE），并通过映射在集群共享内存中的队列，形成可重构的多样化脉动拓扑。为此，我们引入了两种低开销的RISC-V ISA扩展——Xqueue和队列链接寄存器（QLR），以支持硬件层面的队列管理。Xqueue扩展支持单指令访问共享内存映射队列，而QLR允许对队列进行隐式自主访问，从而免去核间显式通信指令的开销。我们在开源多核集群MemPool（含256个PE）上验证了Xqueue和QLR，并分析了混合脉动-共享内存架构在矩阵乘法、卷积和FFT内核中的性能权衡。在面积仅增加6%的情况下，该混合架构将计算单元利用率提升至95%（几乎翻倍），并显著改善能效，使PE功耗占比高达63%。在22nm FDX工艺的典型条件（TT/0.80V/25℃）下，该混合架构以600MHz频率运行且无频率降级，相比共享内存基线架构能效提升达64%，峰值能效达208GOPS/W。