General-purpose NPUs execute fine-grained command DAGs across heterogeneous compute and memory-transfer engines backed by finite, explicitly managed on-chip memories. This execution model creates a directed dependency between scheduling and memory planning: different legal topological orders induce different lifetime overlap, placement opportunities, and spill behavior, while a materialized layout introduces physical-address reuse constraints absent from the input precedence DAG. Command order therefore shapes the feasible memory plan, and the realized plan in turn defines the legal space for subsequent timing refinement. We present LATTICE, a deterministic constraint-directed compiler pipeline. Memory-Pressure-Aware Topological Scheduling reshapes lifetime geometry before address binding; Deterministic Linear Repackaging materializes tiered placement, spill/reload events, and plan-induced reuse constraints; and Critical Path Enhancement recovers pipeline parallelism while preserving the selected memory plan. Every accepted schedule passes independent memory and timing verification. Across six artifact-provided command traces labeled as derived from a Da Vinci NPU flow, LATTICE achieves the best or tied-best result in all 24 evaluated workload-metric comparisons. Relative to the best evaluated baseline for each workload and metric, it reduces peak memory, extra DDR traffic, spill count, and modeled makespan by 18.3% lower, 20.4% lower, 14.1% lower, and 16.3% lower, respectively. Plan-preserving CPE further reduces makespan by 12.1% over Freeze while leaving placement and memory traffic unchanged, establishing the static memory plan as a verifiable scheduling contract between memory planning and pipeline optimization.

翻译：暂无翻译