The deployment of Artificial Intelligence on edge devices (TinyML) is often constrained by the high power consumption and latency associated with traditional Artificial Neural Networks (ANNs) and their reliance on intensive Matrix-Multiply (MAC) operations. Neuromorphic computing offers a compelling alternative by mimicking biological efficiency through event-driven processing. This paper presents the design and implementation of a cycle-accurate, hardware-oriented Spiking Neural Network (SNN) core implemented in SystemVerilog. Unlike conventional accelerators, this design utilizes a Leaky Integrate-and-Fire (LIF) neuron model powered by fixed-point arithmetic and bit-wise primitives (shifts and additions) to eliminate the need for complex floating-point hardware. The architecture features an on-chip Poisson encoder for stochastic spike generation and a novel active pruning mechanism that dynamically disables neurons post-classification to minimize dynamic power consumption. We demonstrate the hardware's efficacy through a fully connected layer implementation targeting digit classification. Simulation results indicate that the design achieves rapid convergence (89% accuracy) within limited timesteps while maintaining a significantly reduced computational footprint compared to traditional dense architectures. This work serves as a foundational building block for scalable, energy-efficient neuromorphic hardware on FPGA and ASIC platforms.

翻译：在边缘设备上部署人工智能（TinyML）常受限于传统人工神经网络（ANNs）的高功耗与高延迟，以及其对密集型矩阵乘法（MAC）运算的依赖。神经形态计算通过模仿生物系统的能效，采用事件驱动处理方式，提供了一种极具吸引力的替代方案。本文提出了一种在SystemVerilog中实现的、周期精确且面向硬件的脉冲神经网络（SNN）核心的设计与实现。与传统加速器不同，该设计采用基于定点运算和按位原语（移位与加法）的泄漏积分发放（LIF）神经元模型，从而无需复杂的浮点硬件。该架构集成了一个用于随机脉冲生成的片上泊松编码器，以及一种新颖的动态剪枝机制，该机制在分类后动态禁用神经元以最小化动态功耗。我们通过一个针对数字分类的全连接层实现来验证该硬件的效能。仿真结果表明，该设计在有限时间步长内实现了快速收敛（89%准确率），同时与传统密集架构相比，显著降低了计算开销。本工作为在FPGA和ASIC平台上构建可扩展、高能效的神经形态硬件提供了基础构建模块。