While 3D IC technology has been extensively explored for ASICs, their application to FPGAs remains limited. Existing studies on 3D FPGAs are often constrained to fixed prototypes, narrow architectural templates, and simulation-only evaluations. In this work, we present LaZagna, the first open-source framework for automated, end-to-end 3D FPGA architecture generation and evaluation. LaZagna supports high-level architectural specification, synthesizable RTL generation, and bitstream production, enabling comprehensive validation of 3D FPGA designs beyond simulation. It significantly broadens the design space compared to prior work by introducing customizable vertical interconnect patterns, novel 3D switch block designs, and support for heterogeneous logic layers. The framework also incorporates practical design constraints such as inter-layer via density and vertical interconnect delay. We demonstrate the capabilities of LaZagna by generating synthesizable RTL that can be taken through full physical design flows for fabric generation, along with functionally correct bitstreams. Furthermore, we conduct five case studies that explore various architectural parameters and evaluate their impact on wirelength, critical path delay, and routing runtime. These studies showcase the framework's scalability, flexibility, and effectiveness in guiding future 3D FPGA architectural and packaging decisions. LaZagna is fully open-source and available on GitHub.

翻译：尽管3D IC技术在ASIC领域已得到广泛探索，但其在FPGA中的应用仍然有限。现有的3D FPGA研究通常受限于固定原型、狭窄的架构模板以及仅限仿真的评估。本工作提出了LaZagna——首个用于自动化端到端3D FPGA架构生成与评估的开源框架。LaZagna支持高层架构规范、可综合RTL生成及比特流生成，能够实现超越仿真的3D FPGA设计全面验证。通过引入可定制的垂直互连模式、创新的3D开关块设计以及对异构逻辑层的支持，该框架显著拓宽了相较于先前工作的设计空间。同时，框架还整合了层间通孔密度与垂直互连延迟等实际设计约束。我们通过生成可综合RTL（可进入完整物理设计流程以生成电路结构）及功能正确的比特流，验证了LaZagna的能力。此外，我们开展了五项案例研究，探索不同架构参数并评估其对线长、关键路径延迟和布线运行时间的影响。这些研究展示了该框架在指导未来3D FPGA架构与封装决策方面的可扩展性、灵活性和有效性。LaZagna已在GitHub上完全开源。