There has been a rise in third-party cloud providers offering quantum hardware as a service to improve performance at lower cost. Although these providers provide flexibility to the users to choose from several qubit technologies, quantum hardware, and coupling maps; the actual execution of the program is not clearly visible to the customer. The success of the user program, in addition to various other metadata such as cost, performance, & number of iterations to converge, depends on the error rate of the backend used. Moreover, the third-party provider and/or tools (e.g., hardware allocator and mapper) may hold insider/outsider adversarial agents to conserve resources and maximize profit by running the quantum circuits on error-prone hardware. Thus it is important to gain visibility of the backend from various perspectives of the computing process e.g., execution, transpilation and outcomes. In this paper, we estimate the error rate of the backend from the original and transpiled circuit. For the forensics, we exploit the fact that qubit mapping and routing steps of the transpilation process select qubits and qubit pairs with less single qubit and two-qubit gate errors to minimize overall error accumulation, thereby, giving us clues about the error rates of the various parts of the backend. We ranked qubit links into bins based on ECR error rates publicly available, and compared it to the rankings derived from our investigation of the relative frequency of a qubit link being chosen by the transpiler. For upto 83.5% of the qubit links in IBM Sherbrooke and 80% in IBM Brisbane, 127 qubit IBM backends, we are able to assign a bin rank which has a difference upto 2 with the bin rank assigned on the basis of actual error rate information.

翻译：随着第三方云服务提供商提供量子硬件即服务以在降低成本的同时提升性能，这一趋势日益显著。尽管这些提供商为用户提供了多种量子比特技术、量子硬件及耦合图的选择灵活性，但程序的实际执行过程对客户而言并不透明。用户程序的成败，除成本、性能、收敛所需迭代次数等多种元数据外，还取决于所使用后端系统的错误率。此外，第三方提供商和/或工具（例如硬件分配器与映射器）可能包含内部/外部对抗性代理，通过在易出错硬件上运行量子电路来节约资源并最大化利润。因此，从计算过程的执行、编译转换及结果等多个维度获取后端系统的可见性至关重要。本文通过原始电路与编译转换后的电路来估计后端错误率。在取证分析中，我们利用编译转换过程中的量子比特映射与路由步骤会选择单量子比特门及双量子比特门错误率较低的量子比特与量子比特对，以最小化总体错误累积这一特性，从而推断后端系统各部分的错误率线索。我们依据公开的ECR错误率将量子比特链路分级归类，并将该分级与通过分析编译器选择各量子比特链路的相对频率所得的排序进行对比。在IBM Sherbrooke（127量子比特后端）中高达83.5%的量子比特链路，以及IBM Brisbane（127量子比特后端）中80%的量子比特链路，我们能够为其分配一个分级等级，该等级与基于实际错误率信息所定等级之差不超过2级。