Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA shows a powerful potential for packet processing. By supporting the P4 language with FPGA processing, network researchers can create customized FPGA-based network functions and execute network tasks on accelerators directly connected to the network. A feature of the P4 language is that it is stateless; however, the FPGA implementation in this research requires state information. This is accomplished using P4 externs to describe the stateful portions of the design and to implement them on the FPGA using High-Level Synthesis (HLS). This paper demonstrates using an FPGA-based SmartNIC to efficiently extract source-destination IP address information from network packets and construct anonymized network traffic matrices for further analysis. The implementation is the first example of the combination of using P4 and HLS in developing network functions on the latest AMD FPGAs. Our design achieves a processing rate of approximately 95 Gbps with the combined use of P4 and High-level Synthesis and is able to keep up with 100 Gbps traffic received directly from the network.

翻译：现场可编程门阵列（FPGAs）凭借其灵活性与高效性，在计算密集型网络处理中发挥着重要作用。特别是借助P4网络编程模型的高层抽象，FPGA在数据包处理方面展现出强大的潜力。通过将P4语言与FPGA处理相结合，网络研究人员能够创建基于FPGA的定制化网络功能，并直接在连接网络的加速器上执行网络任务。P4语言的一个特性是其无状态性；然而，本研究中基于FPGA的实现需要状态信息。这通过使用P4外部函数来描述设计中的有状态部分，并利用高层次综合（HLS）在FPGA上实现它们来完成。本文展示了如何利用基于FPGA的智能网卡高效地从网络数据包中提取源-目的IP地址信息，并构建匿名网络流量矩阵以供进一步分析。该实现是首个在最新AMD FPGA上结合使用P4与HLS开发网络功能的示例。我们的设计通过结合使用P4与高层次综合，实现了约95 Gbps的处理速率，并能跟上直接从网络接收的100 Gbps流量。