Centralized automotive architectures increasingly consolidate compute-intensive workloads onto heterogeneous Multi-Processor System-on-Chip (MPSoC), creating strict execution, memory, and communication constraints. This paper presents RunSoC 2.0, a customizable framework for early-stage design-space exploration of task scheduling and allocation on heterogeneous MPSoCs. Building on RunSoC 1.0, which targeted allocation on homogeneous hardware, RunSoC 2.0 extends the framework to heterogeneous platforms by modeling processor-specific execution times, cluster-level organization, and domain-specific processing properties. It represents task sets as directed acyclic graphs (DAGs) subjected to strict end-to-end latency and core-affinity constraints, and formulates task scheduling and allocation as a multi-objective optimization problem that minimizes hierarchical memory-budget violations and inter-core/inter-cluster communication penalties. The framework supports multiple solving backends, including COIN-OR Branch and Cut (CBC), Google OR-Tools CP-SAT, and a Genetic Algorithm (GA), enabling comparative evaluation of exact, constraint-programming, and meta-heuristic approaches. We evaluate RunSoC 2.0 using synthetic automotive task sets ranging from 10 to 500 tasks, mapped to representative heterogeneous MPSoCs, including the Renesas R-Car V4H, NVIDIA Jetson AGX Orin, and TI TDA4VM. The results show that RunSoC 2.0 can generate feasible and optimal schedules, expose architectural bottlenecks, and support rapid comparison of platform alternatives. Notably, CP-SAT consistently outperforms both CBC and the GA across tightly constrained hard real-time scheduling instances. By incorporating cluster-aware communication and memory modeling, RunSoC 2.0 improves the realism of early-stage MPSoC analysis while retaining practical solution times for large automotive workloads. (..)

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