The complexity of modern hardware designs necessitates advanced methodologies for optimizing and analyzing modern digital systems. In recent times, machine learning (ML) methodologies have emerged as potent instruments for assessing design quality-of-results at the Register-Transfer Level (RTL) or Boolean level, aiming to expedite design exploration of advanced RTL configurations. In this presentation, we introduce an innovative open-source framework that translates RTL designs into graph representation foundations, which can be seamlessly integrated with the PyTorch Geometric graph learning platform. Furthermore, the Verilog-to-PyG (V2PYG) framework is compatible with the open-source Electronic Design Automation (EDA) toolchain OpenROAD, facilitating the collection of labeled datasets in an utterly open-source manner. Additionally, we will present novel RTL data augmentation methods (incorporated in our framework) that enable functional equivalent design augmentation for the construction of an extensive graph-based RTL design database. Lastly, we will showcase several using cases of V2PYG with detailed scripting examples. V2PYG can be found at \url{https://yu-maryland.github.io/Verilog-to-PyG/}.

翻译：现代硬件设计的复杂性需要先进的方法来优化和分析数字系统。近年来，机器学习方法已成为在寄存器传输级（RTL）或布尔级评估设计质量结果的有力工具，旨在加速先进RTL配置的设计探索。本文介绍一个创新的开源框架，该框架将RTL设计转化为图表示基础，可与PyTorch Geometric图学习平台无缝集成。此外，Verilog-to-PyG（V2PYG）框架兼容开源电子设计自动化工具链OpenROAD，支持以完全开源的方式收集标注数据集。我们还将介绍框架中内置的新型RTL数据增强方法，通过功能等价的设计增强来构建大规模基于图的RTL设计数据库。最后，我们通过详细的脚本示例展示V2PYG的多个应用场景。V2PYG开源地址：\url{https://yu-maryland.github.io/Verilog-to-PyG/}。