Fully-analog in-memory computing (IMC) architectures that implement both matrix-vector multiplication and non-linear vector operations within the same memory array have shown promising performance benefits over conventional IMC systems due to the removal of energy-hungry signal conversion units. However, maintaining the computation in the analog domain for the entire deep neural network (DNN) comes with potential sensitivity to interconnect parasitics. Thus, in this paper, we investigate the effect of wire parasitic resistance and capacitance on the accuracy of DNN models deployed on fully-analog IMC architectures. Moreover, we propose a partitioning mechanism to alleviate the impact of the parasitic while keeping the computation in the analog domain through dividing large arrays into multiple partitions. The SPICE circuit simulation results for a 400 X 120 X 84 X 10 DNN model deployed on a fully-analog IMC circuit show that a 94.84% accuracy could be achieved for MNIST classification application with 16, 8, and 8 horizontal partitions, as well as 8, 8, and 1 vertical partitions for first, second, and third layers of the DNN, respectively, which is comparable to the ~97% accuracy realized by digital implementation on CPU. It is shown that accuracy benefits are achieved at the cost of higher power consumption due to the extra circuitry required for handling partitioning.

翻译：在同一内存阵列内实施矩阵-矢量倍增和非线性矢量操作的全成模拟计算(IMC)结构显示,由于消除了能量饥饿信号转换装置,对传统的闭路电视系统产生有希望的性能效益;然而,在整个深神经网络(DNN)的模拟域中维持模拟计算,可能会对连接寄生虫形成敏感;因此,在本文件中,我们调查了电路寄生虫阻力和功能性能对在完全模拟的IMC结构中部署的DNN模型的准确性的影响;此外,我们提议了一个分层机制,以减轻寄生虫模型的影响,同时通过将大型阵列分成多个分区,将计算留在模拟域内。在全深神经网络(DNNN)中安装的400 X 120 X 84 X 10 DNNN 模拟模型的模拟结果显示,在完全analog IMC 电路路段上安装的400 X 120 X 84 X 10 DNNNM 电路段,可以达到94.84% 的精确度,在16、8 和8 横向分区应用中可以达到8个DNNT第一、二、第三层和第三层的垂直隔断隔断点,而实现的电路段。