Hardware event counters offer the potential to reveal not only performance bottlenecks but also detailed microarchitectural behavior. In practice, this promise is undermined by their vague specifications, opaque designs, and multiplexing noise, making event counter data hard to interpret. We introduce CounterPoint, a framework that tests user-specified microarchitectural models - expressed as $μ$path Decision Diagrams - for consistency with performance counter data. When mismatches occur, CounterPoint pinpoints plausible microarchitectural features that could explain them, using multi-dimensional counter confidence regions to mitigate multiplexing noise. We apply CounterPoint to the Haswell Memory Management Unit as a case study, shedding light on multiple undocumented and underdocumented microarchitectural behaviors. These include a load-store queue-side TLB prefetcher, merging page table walkers, abortable page table walks, and more. Overall, CounterPoint helps experts reconcile noisy hardware performance counter measurements with their mental model of the microarchitecture - uncovering subtle, previously hidden hardware features along the way.

翻译：硬件事件计数器不仅能够揭示性能瓶颈，还能展现详细的微架构行为。然而在实践中，由于规范模糊、设计不透明以及多路复用噪声等问题，事件计数器数据的可解释性受到严重制约。本文提出CounterPoint框架，该框架能够检验用户指定的微架构模型——以$μ$路径决策图形式表达——与性能计数器数据的一致性。当出现不匹配时，CounterPoint通过构建多维计数器置信区间来抑制多路复用噪声，进而定位可能解释这些差异的微架构特征。我们以Haswell内存管理单元为案例进行研究，揭示了多个未记录或文档不全的微架构行为，包括加载-存储队列侧TLB预取器、可合并的页表遍历器、可中止的页表遍历机制等。总体而言，CounterPoint帮助专家将带噪声的硬件性能计数器测量结果与其对微架构的心智模型相校准，并在此过程中发现那些细微且此前未被察觉的硬件特性。