We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) open, we show that it is possible to disturb DRAM cells through a DRAM column (i.e., bitline) and induce bitflips in DRAM cells sharing the same columns as the aggressor row (across multiple DRAM subarrays). With ColumnDisturb, the activation of a single row concurrently disturbs cells across as many as three subarrays (e.g., 3072 rows) as opposed to RowHammer/RowPress, which affect only a few neighboring rows of the aggressor row in a single subarray. We rigorously characterize ColumnDisturb and its characteristics under various operational conditions using 216 DDR4 and 4 HBM2 chips from three major manufacturers. Among our 27 key experimental observations, we highlight two major results and their implications. First, ColumnDisturb affects chips from all three major manufacturers and worsens as DRAM technology scales down to smaller node sizes (e.g., the minimum time to induce the first ColumnDisturb bitflip reduces by up to 5.06x). We observe that, in existing DRAM chips, ColumnDisturb induces bitflips within a standard DDR4 refresh window (e.g., in 63.6 ms) in multiple cells. We predict that, as DRAM technology node size reduces, ColumnDisturb would worsen in future DRAM chips, likely causing many more bitflips in the standard refresh window. Second, ColumnDisturb induces bitflips in many (up to 198x) more rows than retention failures. Therefore, ColumnDisturb has strong implications for retention-aware refresh mechanisms that leverage the heterogeneity in cell retention times: our detailed analyses show that ColumnDisturb greatly reduces the benefits of such mechanisms.

翻译：我们通过实验在真实商用DRAM芯片中验证了一种新型广泛存在的读取干扰现象——ColumnDisturb。通过重复打开或持续保持某DRAM行（攻击行）为开启状态，我们证明能够通过DRAM列（即位线）干扰DRAM存储单元，并在与攻击行共享相同列（跨越多个DRAM子阵列）的存储单元中诱发比特翻转。与仅影响单个子阵列中攻击行相邻少数行的RowHammer/RowPress不同，ColumnDisturb现象中单行的激活可同时干扰多达三个子阵列（例如3072行）的存储单元。我们使用来自三大制造商的216颗DDR4与4颗HBM2芯片，系统性地表征了ColumnDisturb在不同工作条件下的特性。在27项关键实验观察中，我们重点阐述两项主要发现及其影响：首先，ColumnDisturb影响所有三大制造商的芯片，且随着DRAM技术节点尺寸缩小（例如首次诱发ColumnDisturb比特翻转的最短时间最多缩短5.06倍），该现象趋于恶化。我们在现有DRAM芯片中观察到，ColumnDisturb可在标准DDR4刷新窗口内（例如63.6毫秒）诱发多个存储单元的比特翻转。我们预测随着DRAM技术节点尺寸减小，ColumnDisturb在未来DRAM芯片中将进一步恶化，很可能在标准刷新窗口内引发更多比特翻转。其次，ColumnDisturb诱发比特翻转的行数远超存储保持失效（最多达198倍）。因此，这对利用存储单元保持时间异质性的感知保持刷新机制具有重要影响：我们的详细分析表明，ColumnDisturb将显著削弱此类机制的优化效果。