In this paper, the SHIP4LLRF (Scalable Hardware Integrated Platform for LLRF) based on 6U VPX-standard was designed preliminarily, which includes 6U mother board and two HPC FPGA mezzanine cards (FMCs). The ADC and DAC FMC is based on ADS54J60 from TI and LTC2000Y-16 form ADI, respectively. The system mother board is based on Xilinx Kintex UltraScale KU060, which also features 64-bit DDR4 SDRAM, QSFP and USB3.0 interfaces. Each FMC connector is assigned 58 pairs of LVDS standard IOs and 8 pairs of GTH high-speed serial lanes. Besides, the mother board is equipped with the self-developed ZYNQBee2 module based on ZYNQ7010 for slow control such as EPICS. All ADC or DAC raw data in each SHIP4LLEF is compressed loss-less without triggering and transmitted to the process board. A scalar quantization method which is in development is used for lossless compression of ADC raw data, the process board will decompress the ADC data and perform a digital algorithm to measure the amplitude and phase of the high frequency signal. This de-sign is scalable for testing and upgradability, mean-while, the trigger-less data transmission enable this system participate in both local (rack-scale) and accelerator-wide communication networks.

翻译：本文对基于6U VPX标准的SHIP4LLRF（可扩展硬件集成平台，用于低电平射频系统）进行了初步设计，包含6U母板和两块HPC FPGA夹层卡（FMC）。ADC与DAC夹层卡分别基于TI公司的ADS54J60和ADI公司的LTC2000Y-16。系统母板采用Xilinx Kintex UltraScale KU060芯片，并配备了64位DDR4 SDRAM、QSFP接口及USB3.0接口。每个FMC连接器分配了58对LVDS标准IO与8对GTH高速串行通道。此外，母板搭载了基于ZYNQ7010的自研ZYNQBee2模块，用于实现EPICS等慢速控制。各SHIP4LLRF模块内的ADC或DAC原始数据均以无触发方式无损压缩后传输至处理板。采用正在研发的标量量化方法对ADC原始数据进行无损压缩，处理板将解压缩ADC数据并执行数字算法，以测量高频信号的幅度与相位。本设计具备可扩展性，便于测试与升级，同时无触发数据传输机制使得该系统可参与本地（机柜级）及加速器级通信网络。