We propose a Clifford noise reduction (CliNR) scheme that provides a reduction of the logical error rate of Clifford circuit with lower overhead than error correction and without the exponential sampling overhead of error mitigation. CliNR implements Clifford circuits by splitting them into sub-circuits that are performed using gate teleportation. A few random stabilizer measurements are used to detect errors in the resources states consumed by the gate teleportation. This can be seen as a teleported version of the CPC scheme, with offline fault-detection making it scalable. We prove that CliNR achieves a vanishing logical error rate for families of $n$-qubit Clifford circuits with size $s$ such that $nsp^2$ goes to 0, where $p$ is the physical error rate, meaning that it reaches the regime $ns = o(1/p^2)$ whereas the direct implementation is limited to $s = o(1/p)$. Moreover, CliNR uses only $3n+1$ qubits, $2s + o(s)$ gates and has zero rejection rate. This small overhead makes it more practical than quantum error correction in the near term and our numerical simulations show that CliNR provides a reduction of the logical error rate in relevant noise regimes.

翻译：我们提出了一种Clifford噪声抑制（CliNR）方案，该方案能够降低Clifford电路的逻辑错误率，其开销低于纠错技术，且避免了误差缓解中存在的指数级采样开销。CliNR通过将Clifford电路拆分为多个子电路并采用门传输方式执行来实现。方案利用少量随机稳定子测量来检测门传输过程中消耗的资源态错误。这可以视为CPC方案的传输版本，其离线故障检测机制保证了可扩展性。我们证明，对于规模为$s$的$n$量子比特Clifford电路族，当$nsp^2$趋近于0时（其中$p$表示物理错误率），CliNR能够实现趋近于零的逻辑错误率，这意味着其可达到$ns = o(1/p^2)$的工作区间，而直接执行方案仅限$s = o(1/p)$。此外，CliNR仅需使用$3n+1$个量子比特和$2s + o(s)$个量子门，且拒绝率为零。这种低开销特性使其在近期比量子纠错更具实用性，数值模拟结果表明CliNR在相关噪声区间内能有效降低逻辑错误率。