In-SRAM computing promises energy efficiency, but circuit nonlinearities and PVT variations pose major challenges in designing robust accelerators. To address this, we introduce OPTIMA, a modeling framework that aids in analyzing bit-line discharge and power consumption in 6T-SRAM-based accelerators. It provides insights into limiting factors and enables fast design-space exploration of circuit configurations. Leveraging OPTIMA for in-SRAM multiplications exhibits ~100x simulation speed-up while maintaining an RMS modeling error of 0.88mV. Exploration yields an optimized multiplier with 1.05pJ energy consumption per 4-bit operation and classification accuracies of 71.8% (top-1) and 90.4% (top-5) for ImageNet and 92.5% for CIFAR-10 datasets respectively when applied in quantized DNNs. To further support research and development, we made our tool flow available open source at https://github.com/sevjaeg/optima.

翻译：存内计算虽有望提升能效，但电路非线性与工艺-电压-温度（PVT）变异给鲁棒加速器设计带来重大挑战。为此，我们提出OPTIMA建模框架，用于分析基于6T-SRAM加速器的位线放电与功耗特性。该框架能揭示性能限制因素，并支持对电路配置进行快速设计空间探索。将OPTIMA应用于存内乘法运算时，在保持0.88mV均方根建模误差的同时，可实现约100倍的仿真加速。通过设计空间探索获得的优化乘法器，其4位运算能耗为1.05pJ；当应用于量化深度神经网络时，在ImageNet数据集上取得71.8%（top-1）与90.4%（top-5）的分类准确率，在CIFAR-10数据集上达到92.5%的准确率。为促进后续研发，我们已将工具链开源发布：https://github.com/sevjaeg/optima。