The increasing complexity of real-time control algorithms and the trend toward 2.5D technology necessitate the development of scalable controllers for managing the complex, integrated operation of chiplets within 2.5D systems-in-package. These controllers must provide real-time computing capabilities and have chiplet-compatible IO interfaces for communication with the controlled components. This work introduces ControlPULPlet, a chiplet-compatible, real-time multi-core RISC-V controller, which is available as an open-source release. It includes a 32-bit CV32RT core for efficient interrupt handling and a specialized direct memory access (DMA) engine to automate periodic sensor readouts. A tightly-coupled programmable multi-core accelerator is integrated via a dedicated AXI4 port. A flexible AXI4-compatible die-to-die (D2D) link supports inter-chiplet communication in 2.5D systems and enables high-bandwidth transfers in traditional 2D monolithic setups. We designed and fabricated ControlPULPlet as a silicon prototype called Kairos using TSMC's 65nm CMOS technology. Kairos executes predictive control algorithms at up to 290 MHz while consuming just 30 mW of power. The D2D link requires only 16.5 kGE in physical area per channel, adding just 2.9% to the total system area. It supports off-die access with an energy efficiency of 1.3 pJ/b and achieves a peak duplex transfer rate of 51 Gb/s per second at 200 MHz.

翻译：实时控制算法日益复杂，加之2.5D技术发展趋势，亟需开发可扩展的控制器来管理2.5D系统级封装内芯粒的复杂集成操作。这类控制器需具备实时计算能力，并拥有与芯粒兼容的输入输出接口，以便与被控组件通信。本文提出ControlPULPlet——一款芯粒兼容的实时多核RISC-V控制器，现已作为开源项目发布。该控制器包含一个32位CV32RT内核以实现高效中断处理，以及一个专用直接内存访问引擎来自动执行周期性传感器读数采集。通过专用AXI4端口集成了紧耦合可编程多核加速器。灵活的AXI4兼容型芯粒间链路支持2.5D系统中的跨芯粒通信，并能在传统2D单片架构中实现高带宽传输。我们采用台积电65纳米CMOS工艺将ControlPULPlet设计并制作为名为Kairos的硅原型芯片。Kairos能以最高290MHz频率执行预测控制算法，功耗仅为30mW。每个通道的芯粒间链路物理面积仅需16.5kGE，仅使系统总面积增加2.9%。该链路支持片外访问时的能效达1.3pJ/比特，在200MHz频率下可实现每秒51Gb/s的峰值双工传输速率。