Turbo-Codes (TC) are a family of convolutional codes enabling Forward-Error-Correction (FEC) while approaching the theoretical limit of channel capacity predicted by Shannons theorem. One of the bottlenecks of a Turbo Encoder (TE) lies in the non-uniform interleaving stage. Interleaving algorithms require stalling the input vector bits before the bit rearrangement causing a delay in the overall process. This paper presents performance enhancement via a parallel algorithm for the interleaving stage of a Turbo Encoder application compliant with the DVB-RCS2 standard. The algorithm efficiently implements the interleaving operation while utilizing attributes of a given DSP. We will discuss and compare a serial model for the TE, with the presented parallel processed algorithm. Results showed a speed-up factor of up to 3.4 Total-Cycles, 4.8 Write and 7.3 Read.

翻译：Turbo码是一类能够逼近香农定理所预测的信道容量理论极限的前向纠错卷积码。Turbo编码器的性能瓶颈之一在于非均匀交织阶段。传统交织算法在进行比特重排前需要暂停输入向量比特流，从而导致整体处理延迟。本文提出了一种面向符合DVB-RCS2标准的Turbo编码器交织阶段的并行算法，该算法通过利用特定数字信号处理器（DSP）的固有属性高效实现交织操作。我们将对比该并行算法与Turbo编码器串行模型的性能差异。实验结果表明，该算法可实现最高3.4倍的总周期加速比、4.8倍的写入加速比以及7.3倍的读取加速比。