LLM-based RTL generation is an interesting research direction, as it holds the potential to liberate the least automated stage in the current chip design. However, due to the substantial semantic gap between high-level specifications and RTL, coupled with limited training data, existing models struggle with generation accuracy. Drawing on human experience, design with verification helps improving accuracy. However, as the RTL testbench data are even more scarce, it is not friendly for LLMs. Although LLMs excel at higher-level languages like Python/C, they have a huge semantic gap from RTL. When implementing the same functionality, Python/C code and hardware code differ significantly in the spatiotemporal granularity, requiring the LLM not only to consider high-level functional semantics but also to ensure the low-level details align with the circuit code. It is not an easy task. In this paper, we propose a function abstracted verifiable middleware (Faver) that streamlines RTL verification in LLM-based workflows. By mixing LLM-friendly code structures with a rule-based template, Faver decouples the details of circuit verification, allowing the LLM to focus on the functionality itself. In our experiments on the SFT model and open-source models, Faver improved the model's generation accuracy by up to 14%.

翻译：基于大型语言模型（LLM）的寄存器传输级（RTL）生成是一个颇具前景的研究方向，因其有望解放当前芯片设计流程中自动化程度最低的环节。然而，由于高层次设计规范与RTL之间存在显著的语义鸿沟，加之训练数据有限，现有模型在生成准确性方面面临挑战。借鉴人类设计经验，采用验证驱动的设计方法有助于提升准确性。但由于RTL测试平台数据更为稀缺，这对LLM并不友好。尽管LLM擅长处理Python/C等高级语言，但这些语言与RTL存在巨大语义差异。在实现相同功能时，Python/C代码与硬件代码在时空粒度上差异显著，要求LLM不仅要考虑高层次功能语义，还需确保底层细节与电路代码相匹配，这并非易事。本文提出一种函数抽象可验证中间件（Faver），该框架通过融合LLM友好的代码结构与基于规则的模板，将电路验证细节解耦，使LLM能够专注于功能实现本身。在监督微调模型与开源模型的实验中，Faver将模型生成准确率最高提升了14%。