The URLLC scenario in the upcoming 6G standard requires low latency and ultra reliable transmission, i.e., error correction towards ML performance. Achieving near-ML performance is very challenging especially for short block lengths. Polar codes are a promising candidate and already part of the 5G standard. The Successive Cancellation List (SCL) decoding algorithm provides very good error correction performance but at the cost of high computational decoding complexity resulting in large latency and low area and energy efficiency. Recently, Automorphism Ensemble Decoding (AED) gained a lot of attention to improve the error correction capability. In contrast to SCL, AED performs several low-complexity (e.g., SC) decoding in parallel. However, it is an open question whether AED can compete with sophisticated SCL decoders, especially from an implementation perspective in state of the art silicon technologies. In this paper we present an elaborated AED architecture that uses an advanced path metric based candidate selection to reduce the implementation complexity and compare it to state of the art SCL decoders in a 12nm FinFET technology. Our AED implementation outperform state of the art SCL decoders by up to 4.4x in latency, 8.9x in area efficiency and 4.6x in energy efficiency, while providing the same or even better error correction performance.

翻译：即将到来的6G标准中的URLLC场景要求低时延和超可靠传输，即实现接近最大似然（ML）性能的纠错能力。达到接近ML的性能极具挑战性，尤其针对短码字长度而言。极化码作为一种有前景的候选方案，已纳入5G标准。连续消除列表（SCL）解码算法提供了出色的纠错性能，但计算解码复杂度高，导致时延大、面积效率和能量效率低。近年来，自同构集成解码（AED）在提升纠错能力方面备受关注。与SCL不同，AED并行执行多个低复杂度（如SC）解码操作。然而，AED能否与先进的SCL解码器相竞争仍是一个开放性问题，尤其是在先进硅技术中的实现视角下。本文提出了一种精细设计的AED架构，采用基于路径度量的高级候选选择方法以降低实现复杂度，并在12nm FinFET技术中与先进的SCL解码器进行比较。我们的AED实现相较于先进的SCL解码器，在时延上最高提升4.4倍、面积效率上提升8.9倍、能量效率上提升4.6倍，同时提供相同甚至更优的纠错性能。