Digital hardware is verified by comparing its behavior against a reference model on a range of randomly generated input signals. The random generation of the inputs hopes to achieve sufficient coverage of the different parts of the design. However, such coverage is often difficult to achieve, amounting to large verification efforts and delays. An alternative is to use Reinforcement Learning (RL) to generate the inputs by learning to prioritize those inputs which can more efficiently explore the design under test. In this work, we present VeRLPy an open-source library to allow RL-driven verification with limited additional engineering overhead. This contributes to two broad movements within the EDA community of (a) moving to open-source toolchains and (b) reducing barriers for development with Python support. We also demonstrate the use of VeRLPy for a few designs and establish its value over randomly generated input signals.

翻译：数字硬件通过将其行为与一系列随机生成输入信号的参考模型进行比较来核查。随机生成投入希望实现对设计不同部分的足够覆盖。然而,这种覆盖往往难以实现,这相当于大量的核查努力和延误。另一个办法是利用强化学习(RL)来生成投入,学习如何优先排序那些可以更有效地探索测试中的设计的投入。在这项工作中,我们向VeRLPy展示了一个开放源码库,允许以有限额外工程间接费用为驱动的核查。这促进了欧洲开发协会内部两种广泛的移动:(a) 转向开放源码工具链,(b) 在Python的支持下减少发展障碍。我们还展示了VeRLPy用于少数设计,并确定其价值超过随机生成输入信号。