Cycle-level simulators such as gem5 are widely used in microarchitecture design, but they are prohibitively slow for large-scale design space explorations. We present Concorde, a new methodology for learning fast and accurate performance models of microarchitectures. Unlike existing simulators and learning approaches that emulate each instruction, Concorde predicts the behavior of a program based on compact performance distributions that capture the impact of different microarchitectural components. It derives these performance distributions using simple analytical models that estimate bounds on performance induced by each microarchitectural component, providing a simple yet rich representation of a program's performance characteristics across a large space of microarchitectural parameters. Experiments show that Concorde is more than five orders of magnitude faster than a reference cycle-level simulator, with about 2% average Cycles-Per-Instruction (CPI) prediction error across a range of SPEC, open-source, and proprietary benchmarks. This enables rapid design-space exploration and performance sensitivity analyses that are currently infeasible, e.g., in about an hour, we conducted a first-of-its-kind fine-grained performance attribution to different microarchitectural components across a diverse set of programs, requiring nearly 150 million CPI evaluations.

翻译：诸如gem5等周期级模拟器在微架构设计中得到广泛应用，但其缓慢的执行速度难以支撑大规模设计空间探索。本文提出Concorde，一种学习快速准确微架构性能模型的新方法。与现有逐指令模拟的仿真器和学习方法不同，Concorde基于捕捉不同微架构组件影响的紧凑型性能分布来预测程序行为。该方法通过简单分析模型推导性能分布，这些模型能估算各微架构组件引发的性能边界，从而为程序在广阔微架构参数空间中的性能特征提供简洁而丰富的表征。实验表明，Concorde比基准周期级模拟器快五个数量级以上，在SPEC、开源及专有基准测试集上的平均每指令周期数预测误差约为2%。这实现了当前难以实现的快速设计空间探索与性能敏感性分析：例如在一小时内，我们完成了对多样化程序集进行微架构组件细粒度性能归因的首创性研究，该研究需要执行近1.5亿次CPI评估。