Known simulations of random access machines (RAMs) or parallel RAMs (PRAMs) by Boolean circuits incur significant polynomial blowup, due to the need to repeatedly simulate accesses to a large main memory. Consider a single modification to Boolean circuits that removes the restriction that circuit graphs are acyclic. We call this the cyclic circuit model. Note, cyclic circuits remain combinational, as they do not allow wire values to change over time. We simulate PRAM with a cyclic circuit, and the blowup from our simulation is only polylogarithmic. Consider a PRAM program $P$ that on a length-$n$ input uses an arbitrary number of processors to manipulate words of size $\Theta(\log n)$ bits and then halts within $W(n)$ work. We construct a size-$O(W(n)\cdot \log^4 n)$ cyclic circuit that simulates $P$. Suppose that on a particular input, $P$ halts in time $T$; our circuit computes the same output within $T \cdot O(\log^3 n)$ gate delay. This implies theoretical feasibility of powerful parallel machines. Cyclic circuits can be implemented in hardware, and our circuit achieves performance within polylog factors of PRAM. Our simulated PRAM synchronizes processors via logical dependencies between wires.

翻译：已知的随机存取机（RAM）或并行随机存取机（PRAM）通过布尔电路的模拟会带来显著的多项式级膨胀，这是由于需要反复模拟对大容量主存的访问。我们考虑对布尔电路进行一项修改，即去除电路图为无环图的限制。我们将此称为循环电路模型。需要指出的是，循环电路仍属于组合逻辑电路，因为它不允许导线值随时间变化。我们利用循环电路模拟PRAM，且该模拟的膨胀仅为多对数级。考虑一个PRAM程序$P$，它在长度为$n$的输入上使用任意数量的处理器来操纵大小为$\Theta(\log n)$比特的字，并在$W(n)$个工作步内停机。我们构建一个规模为$O(W(n)\cdot \log^4 n)$的循环电路来模拟$P$。假设在特定输入下，$P$在时间$T$内停机；我们的电路在$T \cdot O(\log^3 n)$的闸延迟内计算出相同输出。这从理论上证明了强大并行机的可行性。循环电路可通过硬件实现，且我们设计的电路在性能上仅与PRAM相差多对数因子。我们模拟的PRAM通过导线间的逻辑依赖关系实现处理器同步。