While interest in the open RISC-V instruction set architecture is growing, tools to assess the security of concrete processor implementations are lacking. There are dedicated tools and benchmarks for common microarchitectural side-channel vulnerabilities for popular processor families such as Intel x86-64 or ARM, but not for RISC-V. In this paper we describe our efforts in porting an Intel x86-64 benchmark suite for cache-based timing vulnerabilities to RISC-V. We then use this benchmark to evaluate the security of three commercially available RISC-V processors, the T-Head C910 and the SiFive U54 and U74 cores. We observe that the C910 processor exhibits more distinct timing types than the other processors, leading to the assumption that code running on the C910 would be exposed to more microarchitectural vulnerability sources. In addition, our evaluation reveals that $65.9\%$ of the vulnerabilities covered by the benchmark exist in all processors, while only $6.8\%$ are absent from all cores. Our work, in particular the ported benchmark, aims to support RISC-V processor designers to identify leakage sources early in their designs and to support the development of countermeasures.

翻译：尽管对开放式RISC-V指令集架构的关注日益增长，但评估具体处理器实现安全性的工具仍然匮乏。针对Intel x86-64或ARM等主流处理器家族，已有专门的微架构侧信道漏洞检测工具与基准测试套件，但RISC-V领域尚存空白。本文阐述了将基于Intel x86-64的缓存时序漏洞基准测试套件移植至RISC-V架构的研究工作。我们运用该基准测试评估了三款商用RISC-V处理器（T-Head C910、SiFive U54和U74内核）的安全性。观测发现C910处理器展现出比其他处理器更丰富的时序类型，由此推测在C910上运行的代码可能面临更多微架构漏洞源的威胁。此外，评估结果显示基准测试涵盖的漏洞中$65.9\%$存在于所有处理器，而仅$6.8\%$在所有内核中均未出现。本研究特别是移植后的基准测试套件，旨在帮助RISC-V处理器设计者早期识别设计中的信息泄露源，并为防护措施的开发提供支持。