Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using collaborative Verilog tools (i.e., syntax checker, simulator, and waveform tracer). Firstly, we propose a task planner that utilizes a novel Task and Circuit Relation Graph retrieval method to construct a holistic plan based on module descriptions. To debug and fix functional errors, we develop a novel and efficient abstract syntax tree (AST)-based waveform tracing tool, which is integrated within the autonomous Verilog completion flow. The proposed methodology successfully generates 94.2% syntactically and functionally correct Verilog code, surpassing the state-of-the-art methods by 33.9% on the VerilogEval-Human v2 benchmark.

翻译：随着现代集成电路复杂度的日益增长，自动化硬件设计能够从工程流程中消除大量人为错误，从而减少设计缺陷。Verilog是一种广泛应用于数字系统设计与建模的硬件描述语言；因此，Verilog代码生成已成为促进设计流程的新兴研究领域之一。本研究提出VerilogCoder，一个用于Verilog代码生成的多人工智能智能体系统，能够自主编写Verilog代码，并利用协同Verilog工具（包括语法检查器、仿真器和波形追踪器）修复语法及功能错误。首先，我们提出一种任务规划器，采用新颖的任务与电路关系图检索方法，基于模块描述构建整体规划方案。为调试和修复功能错误，我们开发了一种新型高效的基于抽象语法树的波形追踪工具，并将其集成到自主Verilog代码生成流程中。所提方法成功生成了94.2%语法和功能均正确的Verilog代码，在VerilogEval-Human v2基准测试中超越现有最优方法33.9%。