The Von Neumann bottleneck, a fundamental challenge in conventional computer architecture, arises from the inability to execute fetch and data operations simultaneously due to a shared bus linking processing and memory units. This bottleneck significantly limits system performance, increases energy consumption, and exacerbates computational complexity. Emerging technologies such as Resistive Random Access Memories (RRAMs), leveraging crossbar arrays, offer promising alternatives for addressing the demands of data-intensive computational tasks through in-memory computing of analog vector-matrix multiplication (VMM) operations. However, the propagation of errors due to device and circuit-level imperfections remains a significant challenge. In this study, we introduce MELISO (In-Memory Linear Solver), a comprehensive end-to-end VMM benchmarking framework tailored for RRAM-based systems. MELISO evaluates the error propagation in VMM operations, analyzing the impact of RRAM device metrics on error magnitude and distribution. This paper introduces the MELISO framework and demonstrates its utility in characterizing and mitigating VMM error propagation using state-of-the-art RRAM device metrics.

翻译：冯·诺依曼瓶颈作为传统计算机体系架构的根本性挑战，源于处理单元与存储单元通过共享总线连接导致取指与数据操作无法同时执行。这一瓶颈严重制约系统性能、增加能耗并加剧计算复杂度。以交叉阵列为基础的阻变随机存取存储器（RRAM）等新兴技术，通过模拟向量-矩阵乘法（VMM）的内存计算，为应对数据密集型计算任务的需求提供了前景广阔的解决方案。然而，由器件与电路层面缺陷导致的误差传播仍是重大挑战。本研究提出MELISO（内存线性求解器）——一个专为RRAM系统设计的端到端VMM基准测试框架。该框架评估VMM运算中的误差传播，分析RRAM器件指标对误差幅度与分布的影响。本文介绍MELISO框架，并通过采用前沿RRAM器件指标，论证其在表征与缓解VMM误差传播方面的实用价值。