Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an increase in embodied emissions, encompassing carbon emissions arising from design, manufacturing, packaging, and other infrastructural activities. While existing research has developed tools to analyze embodied carbon at the computer architecture level for traditional monolithic systems, these tools do not apply to near-mainstream heterogeneous integration (HI) technologies. HI systems offer significant potential for sustainable computing by minimizing carbon emissions through two key strategies: ``reducing" computation by reusing pre-designed chiplet IP blocks and adopting hierarchical approaches to system design. The reuse of chiplets across multiple designs, even spanning multiple generations of integrated circuits (ICs), can substantially reduce embodied carbon emissions throughout the operational lifespan. This paper introduces a carbon analysis tool specifically designed to assess the potential of HI systems in facilitating greener VLSI system design and manufacturing approaches. The tool takes into account scaling, chiplet and packaging yields, design complexity, and even carbon overheads associated with advanced packaging techniques employed in heterogeneous systems. Experimental results demonstrate that HI can achieve a reduction of embodied carbon emissions up to 70\% compared to traditional large monolithic systems. These findings suggest that HI can pave the way for sustainable computing practices, contributing to a more environmentally conscious semiconductor industry.

翻译：几十年来在能效和低功耗设计方面的进步已成功降低了半导体行业的运营碳足迹。然而，这却导致隐含碳排放增加，涵盖设计、制造、封装及其他基础设施活动所产生的碳排放。现有研究虽已开发出在计算机架构层面分析传统单片系统隐含碳的工具，但这些工具并不适用于接近主流的异构集成技术。异构集成系统通过两项关键策略实现可持续计算的巨大潜力：通过复用预设计芯粒IP模块“减少”计算，并采用层次化系统设计方法。跨多个设计（甚至跨越数代集成电路）复用芯粒，可显著降低其整个使用寿命期间的隐含碳排放。本文介绍了一款专为评估异构集成系统在推动绿色超大规模集成电路设计与制造方法中潜力的碳分析工具。该工具综合考虑了缩放效应、芯粒与封装良率、设计复杂度，甚至异构系统中先进封装技术带来的碳开销。实验结果表明，与传统大型单片系统相比，异构集成可减少高达70%的隐含碳排放。这些发现表明，异构集成能够为可持续计算实践铺平道路，助力构建更环保的半导体行业。