This paper presents GraphAGILE, a domain-specific FPGA-based overlay accelerator for graph neural network (GNN) inference. GraphAGILE consists of (1) \emph{a novel unified architecture design} with an \emph{instruction set}, and (2) \emph{a compiler} built upon the instruction set that can quickly generate optimized code. Due to the proposed instruction set architecture (ISA) and the compiler, GraphAGILE does not require any FPGA reconfiguration when performing inference on various GNN models and input graphs. For the architecture design, we propose a novel hardware module named Adaptive Computation Kernel (ACK), that can execute various computation kernels of GNNs, including general matrix multiplication (GEMM), sparse-dense matrix multiplication (SpDMM) and sampled dense-dense matrix multiplication (SDDMM). The compiler takes the specifications of a GNN model and the graph meta data (e.g., the number of vertices and edges) as input, and generates a sequence of instructions for inference execution. We develop the following compiler optimizations to reduce inference latency: (1) computation order optimization that automatically reorders the computation graph to reduce the total computation complexity, (2) layer fusion that merges adjacent layers to reduce data communication volume, (3) data partitioning with a partition-centric execution scheme that partitions the input graph to fit the available on-chip memory of FPGA, (4) kernel mapping that automatically selects execution mode for ACK, and performs task scheduling to overlap computation with data communication and achieves dynamic load balance. We implement GraphAGILE on a state-of-the-art FPGA platform, Xilinx Alveo U250. GraphAGILE can execute widely used GNN models, including GCN, GAT, GIN, GraphSAGE, SGC and other GNN models supported by GraphGym.

翻译：本文提出GraphAGILE——一种基于FPGA的领域专用覆盖加速器，用于图神经网络（GNN）推理。GraphAGILE由两部分构成：（1）新型统一架构设计，配备指令集；（2）基于该指令集构建的编译器，可快速生成优化代码。得益于所提出的指令集架构（ISA）及编译器，GraphAGILE在执行不同GNN模型和输入图推理时无需重新配置FPGA。在架构设计方面，我们提出一种名为自适应计算核（ACK）的新型硬件模块，能够执行GNN的各类计算核，包括通用矩阵乘法（GEMM）、稀疏-稠密矩阵乘法（SpDMM）和采样稠密-稠密矩阵乘法（SDDMM）。编译器以GNN模型规格和图元数据（如顶点数与边数）为输入，生成推理执行的指令序列。我们开发了以下编译器优化技术以降低推理延迟：（1）计算顺序优化——自动重排计算图以降低总计算复杂度；（2）层融合——合并相邻层以减少数据通信量；（3）数据分区——采用以分区为中心的执行方案，将输入图分割以适配FPGA可用片上内存；（4）内核映射——自动选择ACK执行模式，并通过任务调度实现计算与数据通信的重叠及动态负载均衡。我们在最先进的FPGA平台Xilinx Alveo U250上实现了GraphAGILE。该加速器可执行广泛使用的GNN模型，包括GCN、GAT、GIN、GraphSAGE、SGC，以及GraphGym支持的其他GNN模型。