Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optimized implementation using Boolean logic gates. State-of-the-art logic synthesis algorithms have a large number of logic minimization heuristics, typically applied sequentially based on human experience and intuition. The choice of the order greatly impacts the quality (e.g., area and delay) of the synthesized circuit. In this paper, we propose INVICTUS, a model-based offline reinforcement learning (RL) solution that automatically generates a sequence of logic minimization heuristics ("synthesis recipe") based on a training dataset of previously seen designs. A key challenge is that new designs can range from being very similar to past designs (e.g., adders and multipliers) to being completely novel (e.g., new processor instructions). %Compared to prior work, INVICTUS is the first solution that uses a mix of RL and search methods joint with an online out-of-distribution detector to generate synthesis recipes over a wide range of benchmarks. Our results demonstrate significant improvement in area-delay product (ADP) of synthesized circuits with up to 30\% improvement over state-of-the-art techniques. Moreover, INVICTUS achieves up to $6.3\times$ runtime reduction (iso-ADP) compared to the state-of-the-art.

翻译：逻辑综合是芯片设计中首要且最关键的步骤。该步骤将用硬件描述语言（如Verilog）编写的芯片规范转换为经布尔逻辑门优化的实现。最先进的逻辑综合算法具有大量逻辑最小化启发式方法，通常基于人类经验和直觉顺序应用。顺序的选择会极大影响综合电路的质量（如面积和延迟）。在本文中，我们提出INVICTUS——一种基于模型的离线强化学习（RL）解决方案，能够基于先前设计的数据集自动生成逻辑最小化启发式方法序列（“综合配方”）。一个关键挑战在于新设计可能既与过去设计高度相似（如加法器和乘法器），也可能完全新颖（如新处理器指令）。与先前工作相比，INVICTUS是首个结合强化学习与搜索方法并联合在线分布外检测器，从而在广泛基准测试中生成综合配方的解决方案。我们的结果表明，综合电路的面积-延迟积（ADP）显著提升，相较于最先进技术最高可实现30%的改进。此外，INVICTUS在等面积-延迟积条件下，相较于现有最优方案可将运行时间降低至原来的$6.3\times$。