In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) like Verilog. Since the RTL design is in the format of HDL code, the standard way to evaluate its quality requires time-consuming subsequent synthesis steps with EDA tools. This time-consuming process significantly impedes design optimization at the early RTL stage. Despite the emergence of some recent ML-based solutions, they fail to maintain high accuracy for any given RTL design. In this work, we propose an innovative pre-synthesis PPA estimation framework named MasterRTL. It first converts the HDL code to a new bit-level design representation named the simple operator graph (SOG). By only adopting single-bit simple operators, this SOG proves to be a general representation that unifies different design types and styles. The SOG is also more similar to the target gate-level netlist, reducing the gap between RTL representation and netlist. In addition to the new SOG representation, MasterRTL proposes new ML methods for the RTL-stage modeling of timing, power, and area separately. Compared with state-of-the-art solutions, the experiment on a comprehensive dataset with 90 different designs shows accuracy improvement by 0.33, 0.22, and 0.15 in correlation for total negative slack (TNS), worst negative slack (WNS), and power, respectively.

翻译：在现代VLSI设计流程中，寄存器传输级（RTL）阶段是设计人员通过Verilog等硬件描述语言（HDL）精确定义设计行为的关键环节。由于RTL设计以HDL代码形式呈现，评估其质量的常规方法需要借助EDA工具执行耗时的后续综合步骤。这种耗时流程严重阻碍了RTL早期阶段的设计优化。尽管近期涌现出一些基于机器学习（ML）的解决方案，但它们在面对任意给定的RTL设计时仍难以保持高精度。本文提出一种创新的预综合PPA评估框架MasterRTL，该框架首先将HDL代码转换为名为简单算子图（SOG）的新型比特级设计表示。通过仅采用单比特简单算子，该SOG被证明是一种能够统一不同设计类型与风格的通用表示形式，且其结构与目标门级网表更为相似，从而缩小了RTL表示与网表之间的差距。除了创新的SOG表示外，MasterRTL还针对时序、功耗和面积分别提出了适用于RTL阶段建模的新型ML方法。与现有最优方案相比，在包含90种不同设计的综合性数据集上的实验表明：在总负时序裕量（TNS）、最差负时序裕量（WNS）和功耗的相关性指标上，MasterRTL分别提升了0.33、0.22和0.15。