The task of logic synthesis is to map a technology-independent representation of an application to hardware-specific operations, taking into account various constraints and trading off different costs associated with the implementation. Constraints may include the target gate library and feasible connectivity, whereas the costs capture, for example, the required chip area and delay. Here we propose to use parallel tempering Monte Carlo to find low-level implementations of a given Boolean function. In contrast to previous work leveraging Markov chain Monte Carlo methods such as simulated annealing, we do not start with an initially correct (but suboptimal) implementation that is then further optimized. Instead, our approach starts with a random logic network that is subsequently modified in order to reduce the error to zero. We apply our method to the task of synthesizing Majority-$n$ in terms of Majority-$3$ gates with and without inverters, aiming for a low Majority-$3$ count. Our method is able to find solutions that are on par or better than previously known solutions. For example, for $n\in\{9,11,13\}$ our approach successfully finds inverter-free implementations using between 7% and 42% fewer Majority-$3$ gates.

翻译：逻辑综合的任务是将与技术无关的应用表示映射到特定硬件的操作，同时考虑各种约束并在实现涉及的不同成本之间进行权衡。约束可能包括目标门库和可行的连接性，而成本则捕捉例如所需芯片面积和延迟等因素。在此，我们提出使用并行退火蒙特卡洛方法来寻找给定布尔函数的低层级实现。与先前利用马尔可夫链蒙特卡洛方法（如模拟退火）的工作不同，我们不从初始正确（但次优）的实现开始，再对其进一步优化。相反，我们的方法从一个随机逻辑网络开始，随后对其进行修改以将误差降至零。我们将该方法应用于使用带或不带反相器的Majority-3门来综合Majority-$n$的任务，旨在降低Majority-3门数量。我们的方法能够找到与已知解决方案相当或更优的结果。例如，对于$n\in\{9,11,13\}$，我们的方法成功找到了无反相器的实现，所使用的Majority-3门数量减少了7%至42%。