Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially-available instruction-tuned Large Language Models (LLMs) such as OpenAI's ChatGPT and Google's Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Given that these `conversational' LLMs perform best when used interactively, we perform a case study where a hardware engineer co-architects a novel 8-bit accumulator-based microprocessor architecture with the LLM according to real-world hardware constraints. We then sent the processor to tapeout in a Skywater 130nm shuttle, meaning that this `Chip-Chat' resulted in what we believe to be the world's first wholly-AI-written HDL for tapeout.

翻译：现代硬件设计始于以自然语言提供的规范说明。硬件工程师随后将这些规范翻译成适当的硬件描述语言（如Verilog），然后进行电路综合。自动化这一翻译过程可以减少工程过程中人为错误的来源。但直到最近，人工智能才展现出基于机器的端到端设计翻译能力。商用指令微调大语言模型（如OpenAI的ChatGPT和Google的Bard）宣称能够生成多种编程语言的代码；但针对它们在硬件设计中的研究仍然缺乏。因此，本文探讨了利用这些大语言模型最新进展进行硬件设计时所面临的挑战和呈现的机遇。鉴于这些“对话式”大语言模型在交互使用时表现最佳，我们进行了一项案例研究：一位硬件工程师根据真实硬件约束条件，与大语言模型共同设计了一种新颖的8位累加器型微处理器架构。随后我们将该处理器送往Skywater 130nm流片线进行流片，这意味着此次“芯片聊天”产生了据我们所知世界上首篇完全由AI编写的用于流片的硬件描述语言。