Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and costly memory accesses, the need for large contiguous memory blocks, and complex OS modifications (for software-managed TLBs). We present Victima, a new software-transparent mechanism that drastically increases the translation reach of the processor by leveraging the underutilized resources of the cache hierarchy. The key idea of Victima is to repurpose L2 cache blocks to store clusters of TLB entries, thereby providing an additional low-latency and high-capacity component that backs up the last-level TLB and thus reduces PTWs. Victima has two main components. First, a PTW cost predictor (PTW-CP) identifies costly-to-translate addresses based on the frequency and cost of the PTWs they lead to. Second, a TLB-aware cache replacement policy prioritizes keeping TLB entries in the cache hierarchy by considering (i) the translation pressure (e.g., last-level TLB miss rate) and (ii) the reuse characteristics of the TLB entries. Our evaluation results show that in native (virtualized) execution environments Victima improves average end-to-end application performance by 7.4% (28.7%) over the baseline four-level radix-tree-based page table design and by 6.2% (20.1%) over a state-of-the-art software-managed TLB, across 11 diverse data-intensive workloads. Victima (i) is effective in both native and virtualized environments, (ii) is completely transparent to application and system software, and (iii) incurs very small area and power overheads on a modern high-end CPU.

翻译：地址转换是数据密集型工作负载的性能瓶颈，原因在于大数据集和不规则访问模式导致频繁的高延迟页表遍历（PTW）。减少PTW的方法包括：(i) 大型硬件TLB 或 (ii) 大型软件管理TLB。然而，这两种方案均有显著缺陷：访问延迟、功耗和面积增加（硬件TLB），以及高昂的内存访问开销、对大连续内存块的需求和复杂的操作系统修改（软件管理TLB）。我们提出Victima，一种全新的软件透明机制，通过利用缓存层次结构中未充分利用的资源大幅提升处理器的地址转换范围。Victima的核心思想是重用L2缓存块来存储TLB条目簇，从而提供一种低延迟、大容量的备份组件以支持末级TLB，进而减少PTW。Victima包含两个主要组件：首先，PTW代价预测器（PTW-CP）根据PTW的频率和代价识别高转换成本的地址；其次，一种TLB感知的缓存替换策略，通过考虑(i) 转换压力（例如末级TLB缺失率）和(ii) TLB条目的重用特性，优先保留缓存层次结构中的TLB条目。评估结果表明，在11种多样化的数据密集型工作负载下，相较于基于四层基数树的基线页表设计，Victima在原生（虚拟化）执行环境中将端到端应用性能平均提升7.4%（28.7%）；相较于当前最先进的软件管理TLB，性能提升6.2%（20.1%）。Victima (i) 在原生和虚拟化环境中均有效，(ii) 对应用和系统软件完全透明，且(iii) 在现代高端CPU上引入的功耗和面积开销极小。