While in the past decade there has been significant progress in open-source synthesis and verification tools and flows, one piece is still missing in the open-source design automation ecosystem: a tool to estimate the power consumption of a design on specific target technologies. We discuss a work-in-progress method to characterize target technologies using generic micro-benchmarks, whose results can be used to establish power models of these target technologies. These models can further be used to predict the power consumption of a design in a given use case scenario (which is currently out of scope). We demonstrate our characterization method on the publicly documented Lattice iCE40 FPGA technology, and discuss two approaches to generating micro-benchmarks which consume power in the target device: simple lookup table (LUT) instantiation, and a more sophisticated instantiation of ring oscillators. We study three approaches to stimulate the implemented micro-benchmarks in hardware: Verilog testbenches, micro-controller testbenches, and pseudo-random linear-feedback-shift-register-(LFSR)-based testing. We measure the power consumption of the stimulated target devices. Our ultimate goal is to automate power measurements for technology characterization; Currently, we manually measure the consumed power at three shunt resistors using an oscilloscope. Preliminary results indicate that we are able to induce variable power consumption in target devices; However, the sensitivity of the power characterization is still too low to build expressive power estimation models.

翻译：尽管过去十年间，开源综合与验证工具及流程取得了显著进展，但开源设计自动化生态系统中仍缺失关键一环：针对特定目标技术评估设计功耗的工具。本文讨论了一种正在进行中的方法，该方法通过通用微基准测试表征目标技术，其测试结果可用于建立这些目标技术的功耗模型。这些模型可进一步用于预测特定应用场景（目前超出本文研究范围）下的设计功耗。我们以公开文档化的Lattice iCE40 FPGA技术为例展示了表征方法，并讨论了两种在目标器件上产生功耗的微基准测试生成方式：简单的查找表（LUT）实例化，以及更复杂的环形振荡器实例化。我们研究了三种在硬件中激励微基准测试的方法：Verilog测试平台、微控制器测试平台，以及基于伪随机线性反馈移位寄存器（LFSR）的测试。通过测量受激励目标器件的功耗，初步结果表明我们能够诱发目标器件的可变功耗；然而，当前功耗表征的灵敏度仍不足以构建具有表达力的功耗估计模型。目前我们通过示波器在三个分流电阻上手动测量功耗，最终目标是为技术表征实现功耗测量的自动化。