Recent years have witnessed the growing popularity of domain-specific accelerators (DSAs), such as Google's TPUs, for accelerating various applications such as deep learning, search, autonomous driving, etc. To facilitate DSA designs, high-level synthesis (HLS) is used, which allows a developer to compile a high-level description in the form of software code in C and C++ into a design in low-level hardware description languages (such as VHDL or Verilog) and eventually synthesized into a DSA on an ASIC (application-specific integrated circuit) or FPGA (field-programmable gate arrays). However, existing HLS tools still require microarchitecture decisions, expressed in terms of pragmas (such as directives for parallelization and pipelining). To enable more people to design DSAs, it is desirable to automate such decisions with the help of deep learning for predicting the quality of HLS designs. This requires us a deeper understanding of the program, which is a combination of original code and pragmas. Naturally, these programs can be considered as sequence data, for which large language models (LLM) can help. In addition, these programs can be compiled and converted into a control data flow graph (CDFG), and the compiler also provides fine-grained alignment between the code tokens and the CDFG nodes. However, existing works either fail to leverage both modalities or combine the two in shallow or coarse ways. We propose ProgSG allowing the source code sequence modality and the graph modalities to interact with each other in a deep and fine-grained way. To alleviate the scarcity of labeled designs, a pre-training method is proposed based on a suite of compiler's data flow analysis tasks. Experimental results on two benchmark datasets show the superiority of ProgSG over baseline methods that either only consider one modality or combine the two without utilizing the alignment information.

翻译：近年来，领域专用加速器（如Google的TPU）在深度学习、搜索、自动驾驶等应用中的普及日益增长。为促进DSA设计，高层次综合（HLS）被广泛应用——开发者可将C/C++形式的高层次软件代码编译为低层次硬件描述语言（如VHDL或Verilog）的设计，并最终在专用集成电路（ASIC）或现场可编程门阵列（FPGA）上综合为DSA。然而，现有HLS工具仍需以编译指示（如并行化和流水线化指令）的形式进行微架构决策。为使更多人能够设计DSA，亟需借助深度学习自动化此类决策，以预测HLS设计的质量。这要求我们更深入地理解程序——即原始代码与编译指示的结合。这类程序可被视为序列数据，大语言模型（LLM）在此可发挥作用。此外，这些程序可被编译并转换为控制数据流图（CDFG），编译器还能提供代码标记与CDFG节点间的细粒度对齐。然而，现有工作要么未能同时利用两种模态，要么以浅层或粗粒度的方式组合二者。我们提出ProgSG，使源代码序列模态与图模态能够以深层细粒度的方式交互。为缓解标注设计数据的稀缺问题，我们提出基于一套编译器数据流分析任务的预训练方法。在两个基准数据集上的实验结果表明，ProgSG优于仅考虑单一模态或未利用对齐信息而简单组合两种模态的基线方法。