As quantum computing matures, there is an increasing need for deeper and longer experiments to characterize quantum devices precisely and higher circuit throughput to validate more domain applications. However, this need is hindered by a memory bottleneck at the quantum control system layer, arising from the limited capacity of on-chip block random-access memory (BRAM) and the non-deterministic latency of dynamic random-access memory (DRAM). To break this bottleneck, we present Ant-Q, a memory hierarchy design for the QubiC 2.0 control system that integrates DRAM with BRAM to support pipelined quantum circuit execution while keeping inter-circuit timing deterministic whenever each circuit outlasts the refill of the next. A switch between command buffers then takes a constant 134 ns and, inside a circuit, acts on the qubit as a 144 ns idle. On the bench, Ant-Q runs deep one- and two-qubit randomized benchmarking beyond the command capacity of the baseline. For circuits with at least 1000 shots, it reduces the time the board spends beyond the circuit execution from 18.91%-104.54% to at most 0.53% of the execution time, and it improves the board-level throughput of 30-circuit batches by 51.06% against a baseline with the same shared tables (59.90% against the stock baseline). On a transmon qubit, Ant-Q executes a 5101-Clifford sequence and acquires uninterrupted 100 s Ramsey records with 0.01 Hz frequency spacing. In simulations, these records detect 1/f frequency noise of 1.37 and 1.62 times lower spectral density than the same records split into the 2.048 s runs of the baseline. The measured spectra resolve no 1/f component and match the measurement floor from 0.1 to 100 Hz. Ant-Q has been merged into the open-source QubiC gateware and software.

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