Network-on-chips (NoCs) are currently a widely used approach for achieving scalability of multi-cores to many-cores, as well as for interconnecting other vital system-on-chip (SoC) components. Each entity in 2D mesh-based NoCs has a router responsible for forwarding packets between the dimensions as well as the entity itself, and it is essentially a 5-port switch. With respect to the routing algorithm, there are important trade-offs between routing performance and the efficiency of overcoming potential deadlocks. Common deadlock avoidance techniques including the turn model usually involve restrictions of certain paths a packet can take at the cost of a higher probability for network congestion. In contrast, deadlock resolution techniques, as well as some avoidance schemes, provide more path flexibility at the expense of hardware complexity, such as by incorporating (or assuming) dedicated buffers. This paper provides a deadlock avoidance algorithm for NoC routers based on output-queues (OQs) or virtual-output queues (VOQs), with a focus on their use on field-programmable gate-arrays (FPGAs). The proposed approach features fewer path restrictions than common techniques, and can be based on existing routing algorithms as a baseline, deadlock-free or not. This requires no modification to the queueing topology, and the required logic is minimal. Our algorithm approaches the performance of fully-adaptive algorithms, while maintaining deadlock freedom.

翻译：片上网络（Network-on-Chips，NoC）是当前实现多核到众核可扩展性以及互连其他关键系统芯片（SoC）组件的广泛采用方法。在基于2D网格的NoC中，每个实体都配有一个负责在维度间及实体自身转发数据包的路由器，该路由器本质上是一个5端口交换设备。就路由算法而言，路由性能与克服潜在死锁的效率之间存在重要权衡。常见的死锁避免技术（如转向模型）通常通过限制数据包可选取的某些路径来运作，但代价是网络拥塞概率升高。相比之下，死锁解决技术及某些避免方案通过增加硬件复杂度（例如引入或假设专用缓冲区）来提供更灵活的路径选择。本文提出了一种面向基于输出队列（OQ）或虚拟输出队列（VOQ）的NoC路由器的死锁避免算法，重点关注其在现场可编程门阵列（FPGA）上的应用。与常见技术相比，该方法对路径的限制更少，且可基于现有路由算法（无论是否具备死锁自由特性）作为基线。该方案无需修改队列拓扑结构，所需逻辑资源极少。我们的算法在保持无死锁特性的同时，性能接近全自适应算法。