High-level synthesis (HLS) refers to the automatic translation of a software program written in a high-level language into a hardware design. Modern HLS tools have moved away from the traditional approach of static (compile time) scheduling of operations to generating dynamic circuits that schedule operations at run time. Such circuits trade-off area utilisation for increased dynamism and throughput. However, existing lowering flows in dynamically scheduled HLS tools rely on conservative assumptions on their input program due to both the intermediate representations (IR) utilised as well as the lack of formal specifications on the translation into hardware. These assumptions cause suboptimal hardware performance. In this work, we lift these assumptions by proposing a new and efficient abstraction for hardware mapping; namely h-GSA, an extension of the Gated Single Static Assignment (GSA) IR. Using this abstraction, we propose a lowering flow that transforms GSA into h-GSA and maps h-GSA into dynamically scheduled hardware circuits. We compare the schedules generated by our approach to those by the state-of-the-art dynamic-scheduling HLS tool, Dynamatic, and illustrate the potential performance improvement from hardware mapping using the proposed abstraction.

翻译：高层次综合（HLS）是指将高级语言编写的软件程序自动转换为硬件设计。现代HLS工具已从传统的静态（编译时）操作调度方法转向生成在运行时调度操作的动态电路。此类电路以面积利用率为代价，换取更高的动态性和吞吐量。然而，现有的动态调度HLS工具中的降级流程由于所采用的中间表示（IR）以及缺乏硬件转换的正式规范，对其输入程序采用了保守假设。这些假设导致硬件性能欠佳。在这项工作中，我们通过提出一种新的高效硬件映射抽象——即h-GSA（门控静态单赋值IR的扩展）——来解除这些假设。利用这一抽象，我们提出了一种将GSA转换为h-GSA并将h-GSA映射到动态调度硬件电路的降级流程。我们将所提方法生成的调度与最先进的动态调度HLS工具Dynamatic生成的调度进行了比较，并展示了使用所提抽象进行硬件映射所带来的潜在性能提升。