Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive electronics technologies. SFQ systems operate at tens of gigahertz with up to three orders of magnitude smaller power as compared to CMOS. In conventional SFQ systems, most gates require clock signal. Each gate should have the fanins with equal logic depth, necessitating insertion of path-balancing (PB) DFFs, incurring prohibitive area penalty. Multiphase clocking is the effective method for reducing the path-balancing overhead at the cost of reduced throughput. However, existing tools are not directly applicable for technology mapping of multiphase systems. To overcome this limitation, in this work, we propose a technology mapping tool for multiphase systems. Our contribution is threefold. First, we formulate a phase assignment as a Constraint Programming with Satisfiability (CP-SAT) problem, to determine the phase of each element within the network. Second, we formulate the path balancing problem as a CP-SAT to optimize the number of DFFs within an asynchronous datapath. Finally, we integrate these methods into a technology mapping flow to convert a logic network into a multiphase SFQ circuit. In our case studies, by using seven phases, the size of the circuit (expressed as the number of Josephson junctions) is reduced, on average, by 59.94 % as compared to the dual (fast-slow) clocking method, while outperforming the state-of-the-art single-phase SFQ mapping tools.

翻译：快速单通量子（RSFQ）是最先进的超导电子技术之一。与CMOS相比，SFQ系统可在数十吉赫兹频率下运行，功耗降低多达三个数量级。在传统SFQ系统中，多数逻辑门需要时钟信号。每个逻辑门的所有扇入必须具有相等的逻辑深度，这导致需要插入路径平衡（PB）DFF，从而带来极大的面积开销。多相时钟技术是降低路径平衡开销的有效方法，但其代价是吞吐率下降。然而，现有工具无法直接适用于多相系统的技术映射。为克服这一局限，本文提出一种面向多相系统的技术映射工具。我们的贡献包含三个方面：第一，将相位分配问题建模为带可满足性的约束规划（CP-SAT）问题，以确定网络中每个元件的相位；第二，将路径平衡问题建模为CP-SAT问题，以优化异步数据通路中DFF的数量；第三，将这些方法集成到技术映射流程中，将逻辑网表转换为多相SFQ电路。案例研究表明，与双相（快-慢）时钟方法相比，采用七相时钟可使电路规模（以约瑟夫森结数量表征）平均降低59.94%，同时性能优于当前最先进的单相SFQ映射工具。