Multi-FPGA systems (MFS) are widely adopted for VLSI emulation and rapid prototyping. In an MFS, FPGAs connect only to a limited number of neighbors through bandwidth-constrained links, so inter-FPGA communication cost depends on network topology. This setting exposes two fundamental limitations of existing MFS-aware partitioning methods: conventional hypergraph partitioners focus solely on cut size and ignore topological structure, and they leave substantial FPGA resources unused due to conservative balance margins. We present RePart, a fully customized multilevel hypergraph partitioning framework for MFS that integrates logic replication with topology-aware optimization. RePart introduces three coordinated innovations across the multilevel pipeline: FPGA-aware dynamic coarsening, heat-value guided assignment, and replication-deletion supported refinement. Extensive experiments on the Titan23 and EDA Elite Challenge Contest benchmarks show that RePart reduces total hop distance by 52.3% on average over state-of-the-art hypergraph partitioners with an 11.1x speedup, and outperforms the EDA Elite Challenge winners. Code is available at: https://github.com/Welement-zyf/RePart.

翻译：多FPGA系统（MFS）广泛应用于超大规模集成电路仿真与快速原型验证。在MFS中，FPGA仅通过带宽受限的链路连接有限数量的相邻节点，因此FPGA间的通信代价取决于网络拓扑结构。这一设置揭示了现有MFS感知划分方法的两个根本局限：传统超图划分器仅关注割集规模而忽视拓扑结构，且由于保守的平衡裕度导致大量FPGA资源闲置。我们提出RePart——一种专为MFS设计的全定制多级超图划分框架，该框架将逻辑复制与拓扑感知优化相结合。RePart在多级流水线中引入三项协同创新：FPGA感知动态粗化、热值引导分配以及复制-删除支持的细化。在Titan23与EDA精英挑战赛基准测试上的大量实验表明，RePart相较现有最优超图划分器平均降低总跳数距离52.3%，实现11.1倍加速，并全面超越EDA精英挑战赛获奖方案。代码开源地址：https://github.com/Welement-zyf/RePart。