Dynamic digital timing analysis is a less accurate but fast alternative to highly accurate but slow analog simulations of digital circuits. It relies on gate delay models, which allow the determination of input-to-output delays of a gate on a per-transition basis. Accurate delay models not only consider the effect of preceding output transitions here but also delay variations induced by multi-input switching (MIS) effects in the case of multi-input gates. Starting out from a first-order hybrid delay model for CMOS two-input NOR gates, we develop a hybrid delay model for Muller C gates and show how to augment these models and their analytic delay formulas by a first-order interconnect. Moreover, we conduct a systematic evaluation of the resulting modeling accuracy: Using SPICE simulations, we quantify the MIS effects on the gate delays under various wire lengths, load capacitances, and input strengths for two different CMOS technologies, comparing these results to the predictions of appropriately parameterized versions of our new gate delay models. Overall, our experimental results reveal that they capture all MIS effects with a surprisingly good accuracy despite being first-order only.

翻译：动态数字时序分析是数字电路高精度但缓慢的模拟仿真的一种精度较低但快速的替代方案。它依赖于门延迟模型，该模型允许基于每次跳变确定门的输入到输出延迟。精确的延迟模型不仅考虑此处先前输出跳变的影响，还考虑多输入门情况下由多输入切换（MIS）效应引起的延迟变化。从CMOS双输入NOR门的一阶混合延迟模型出发，我们为Muller C门开发了一种混合延迟模型，并展示了如何通过一阶互连来增强这些模型及其解析延迟公式。此外，我们对所得建模精度进行了系统评估：通过使用SPICE仿真，我们量化了在两种不同CMOS技术下，不同导线长度、负载电容和输入强度条件下MIS效应对门延迟的影响，并将这些结果与我们新门延迟模型适当参数化版本的预测进行比较。总体而言，我们的实验结果表明，尽管仅为一阶模型，它们却能以惊人的良好精度捕捉所有MIS效应。